Design and Implementation of Low Power High Speed VLSI DSP System for Multirate Polyphase Interpolator

Interpolator is an important sampling device used for Multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Recent advances in mobile computing and communication applications demand low power and high speed VLSI DSP systems. In this paper, an efficient method has been presented to implement low power high speed Multirate Polyphase Interpolator for wireless communication systems. Many architecture developed for the design of low complexity, bit parallel Multiple Constant Multiplications operation which dominates the complexity of DSP systems. However, major drawbacks of present approaches are either too costly or not efficient enough. On the other hand, MCM and digit-serial adder offer alternative low complexity designs, since digit-serial architecture occupy less area and are independent of the data word length. Multiple Constant Multiplications is efficient way to reduce the number of addition and subtraction in polyphase filter implementation. The simulation of parameters is analyzed by using synopsis 45 nm and Xilinx. Experimental results have shown the efficiency of the proposed technique and the analysis of different architecture. This Multirate design methodology is systematic and applicable to many problems.